The present invention relates to solid state image sensors using CMOS technology.
Solid state image sensors using CMOS technology may suffer from fixed pattern noise because of variations in characteristics between pixels. Fixed pattern noise has been reduced by using a correlated double sampling (CDS). This requires that each pixel be read twice, as discussed in more detail below. This technique is satisfactory for many purposes, but increases circuit size and complexity and leads to additional noise.
Referring to FIG. 1, the conventional mode of operation of an active pixel array is shown. By way of example, a 3xc3x973 array is illustrated. Each pixel 10 includes a photodiode 12, and a transistor pair 14. The transistor pair 14 forms the upper half of an NMOS source follower structure, and the lower half of the NMOS source follower structure is formed by a transistor Mx in the column line 16.
The source follower structure buffers the photodiode voltage onto the column line 16, which has a capacitance. The output voltage is then processed by a correlated double sampling in the column sampling and readout circuitry 18. This requires that the pixel be read twice. First, the light-induced signal voltage is read. Then, the pixel is reset and the pixel reset voltage is read. The signal output by the column sampling and readout circuitry 18 is the difference between these voltages. The pixels receive power and reset voltage from a regulated power supply via lines VRT arranged in the same direction as the rows.
This prior art arrangement requires two sampling steps, and uses two capacitors to hold the samples in each column. The subtraction of Vrst from Vsig removes low frequency pixel noise and thus reduces fixed pattern noise, but increases high frequency noise. The need for two capacitors increases the column area and contributes thermal (kT/C) noise.
The present invention provides a solid state image sensor comprising an array of pixels arranged in rows and columns on a semiconductor substrate for defining an image plane. The pixels of each column are connected to a respective first column conductor. Each pixel includes a photodiode, a capacitance for integrating light-induced current through the photodiode, a reset switch and a switching element for connecting the voltage on the capacitance to the respective first column conductor.
Each column has a second column conductor connected to the pixel reset switches. The first and second column conductors of each column are connected to a respective read-reset circuit that operates in a first reset mode in which a predetermined reset voltage is applied to the second column conductor, and operates in a second read mode in which pixel signal voltages are read from the first column conductor.